The present invention relates to an improved semiconductor memory and to an improved testing method therefor.
A typical semiconductor memory as shown in FIG. 2 has a memory cell array 1 consisting of a large number of memory cells 2 (though only four are shown in the drawing) arranged in rows and columns. Each of the memory cells 2 has a memory cell transistor 2a and a memory cell capacitor 2b. In a DRAM (Dynamic RAM), the memory cell transistor 2a is composed of an N-channel MOS transistor. Word lines 3 (only two are shown in the drawing) are provided for the individual rows of the memory cell array 1 such that the memory cells 2 aligned in each of the rows are connected to the corresponding one of the word lines 3. Bit lines 4 (only two are shown in the drawing) are provided for the individual columns of the memory cell array 1 such that the memory cells 2 aligned in each of the columns are connected to the corresponding one of the bit lines 4. A row decoder 5 selects among the word lines 3, while a column decoder 6 selects among the bit lines 4. An I/O interface 7 is connected to each of the decoders 5 and 6 to receive an address signal for specifying the word line 3 and bit line 4 to be selected and a control signal such as /RAS (Row Address Strobe).
The DRAM has used a circuit for boosting a potential on the selected word line over an external power-supply voltage to prevent a write voltage supplied to the memory cell from lowering due to the threshold voltage of the gate of the N-channel MOS memory cell transistor 2a.
To boost the potential on the selected word line over the power-supply voltage, there has been used a conventional method wherein a voltage is boosted by using a capacitor in activating the word line, i.e., in generating a word-line drive signal so that the voltage level of the word-line drive signal is thereby boosted over the power-supply voltage.
In accordance with the conventional method wherein the voltage is boosted by using the capacitor only when the word-line drive signal is generated, the word-line drive signal is disconnected from a power supply and placed in a floating state when the voltage level of the word-line drive signal has been boosted over the power-supply voltage as a result of voltage boosting performed by using the capacitor. However, if there is a leakage current resulting from a defect and allowed to flow from the word line to another node, the potential on the word line lowers, which prevents the writing of data in the memory cell. To avoid this, an additional word-line-potential holding circuit may also be provided to hold the word-line potential on the "High" level by pumping the word-line drive signal to such a degree as to compensate for the leakage current.
In this case, if the leakage current is slightly larger in quantity than the current supplied by pumping for holding the potential on the word line, the voltage on the word line may gradually lower since pumping is constantly performed when the word line is active. Although such a memory should be judged faulty and removed as a result of testing, testing requires a cycle time equal to or longer than a maximum cycle time defined in specifications, which increases a testing time as well as testing cost. Even when the leakage current is slightly smaller in quantity than the supplied current, if the leakage current has been caused by a defect resulting from a broken oxide film or the like, the defect has the potential to increase the leakage current, cause malfunction, and degrade the reliability of the product as it deteriorates with time.
To overcome the problem, Japanese Unexamined Patent Publication No. 4-252488, for example, has proposed a method wherein the operation of the word-line-potential holding circuit is halted at the time of testing by an additional circuit which uses a test signal to halt the operation of an oscillator for pumping.
On the other hand, there has recently been adopted a method wherein a word-line drive signal is generated by using an internal boosted power supply obtained by preliminary pumping, which is for eliminating a delay in operating speed resulting from voltage boosting performed by using a capacitor on the rising edge of the word-line drive signal. The method provides an increased operating speed, since voltage boosting has been performed by using the capacitor prior to the rising edge of the word-line drive signal and hence it is no more necessary to perform voltage boosting by using the capacitor on the rising edge of the word-line drive signal.
In accordance with the method wherein the word-line drive signal is generated by using the internal boosted power supply obtained by preliminarily generating a boosted voltage by pumping, the boosted power supply may have sufficiently high current drive capability so that a defect resulting from the leakage current flowing from the word line as described above need not be considered conventionally.